There are always three to four polysilicon (poly-Si or poly) layers required for commodity dynamic random access memory (DRAM). It is not very friendly for LOGIC foundry fabrication and it is very difficult to merge with high performance LOGIC process for so-called system-on-chip (SOC).
U.S. Pat. No. 6,177,697 B1 to Cunningham describes a single polysilicon process for a DRAM using a trench capacitor formed from poly 1— same as the gate.
U.S. Pat. No. 4,907,047 to Kato et al. describes a memory device having a trench capacitor.
U.S. Pat. No. 5,793,075 to Alsmeier et al. describes an integrated circuit capacitor that achieves a high capacitance by using an inversion layer in the substrate as the plate counter electrode for the capacitor.
U.S. Pat. No. 5,574,621 to Sakamoto et al. describes a capacitor for an integrated circuit having a conductive trench disposed below a bottom electrode layer that electrically connects to the bottom electrode layer to a semiconductor substrate.
U.S. Pat. No. 5,208,657 to Chatterjee et al. describes a DRAM cell and array of cells, together with a method of fabrication, wherein the cell includes one field effect transistor (FET) and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate.